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82511 sy/d2706 ms im 20060831-s00005 / 92706 / d0205 mh ot b8-8935 no.8321-1/30 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 lb11600jv overview the lb11600jv is a direct pwm drive predriver ic appropriate for 3-phase power brushless motors in automotive applications. this ic can implement either high side pwm drive or low side pwm drive motor driver circuits depending on the configuration of the output circuits, which use discrete transistors such as mosfets or bipolar transistors. in addition to a full complement of protectio n functions, including overcurrent, thermal, motor constraint, and undervoltage protection, the lb11600jv also provides an integrated speed control function. thus the lb11600jv can implement high reliability/high functionality drive circuits. functions ? three-phase bipolar drive (uh, vh, and wh pins, pwm control) ? forward/reverse switching circuit ? overcurrent protection circuit ? undervoltage protection circuit ? motor constraint protection circuit ? thermal protection circuit ? speed control circuit specifications absolute maximum ratings at ta = 25 c parameter symbol conditions rated value unit supply voltage v cc max v cc pin 14.5 v output circuit current i o max ul, vl, wl, uh, vh, and wh pins 40 ma allowable power dissipation pd max independent ic 0.5 w operating temperature topr -40 to 100 c storage temperature tstg -55 to 150 c ordering number : EN8321b monolithic digital ic brushless motor predriver ic for automotive applications stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lb11600jv no.8321-2/30 allowable operating ranges at ta = 25 c parameter symbol conditions rated value unit v cc voltage supply voltage range v cc v cc pin 4.5 to 14 v output current v cc op ul, vl, wl, uh, vh, and wh pins 30 ma rf pin voltage vrf 0 to 3 v hp pin voltage vhp 0 to 14 v hp pin voltage ihp 0 to 10 ma electrical characteristics at ta = 25 c, v cc = 5v rated value parameter symbol conditions min. typ. max. unit current drain 1 i cc 1 s/s = 0v 13 20 27 ma current drain 2 i cc 2 stop mode, s/s = 5v 1.5 2.5 3.5 ma output block output voltage 1-1 v out 1-1 low level, io = 400a 0.1 0.3 v output voltage 1-2 v out 1-2 low level, io = 10ma 0.8 1.1 v output voltage 2 v out 2 high level, io = -20ma v cc -1.1 v cc -0.9 v hall amplifier block input bias current ihb (ha) -2 -0.5 a common-mode input voltage range 1 vicm1 when a hall effect element is used 0.5 v cc -2.0 v common-mode input voltage range 2 vicm2 when a single-sided input bias is used (hall ic applications) 0 v cc v hall input sensitivity 80 mv p-p hysteresis vin (ha) 15 24 40 mv input voltage (low high) vslh (ha) 5 12 20 mv input voltage (high low) vshl (ha) -20 -12 -5 mv toc pin input voltage 1 vtoc1 output duty: 100% 2.72 3.0 3.30 v input voltage 2 vtoc2 output duty: 0% 1.15 1.35 1.55 v input voltage 1l vtoc1l when v cc = 4.7v output duty: 100% 2.5 2.80 3.1 v input voltage 2l vtoc2l when v cc = 4.7v, output duty: 0% 1.05 1.24 1.43 v input voltage 1h vtoc1h when v cc = 5.3v, output duty: 100% 2.88 3.20 3.52 v input voltage 2h vtoc2h when v cc = 5.3v, output duty: 0% 1.17 1.38 1.59 v ctl pin input offset voltage v io (cont) -10 10 mv input bias current ib (cont) -1 1 a common-mode input voltage range vicm 0 v cc -1.7 v high-level output voltage v oh (cont) itoc = -0.2ma v cc -1.1 v cc -0.8 v low-level output voltage v ol (cont) itoc = 0.2ma 0.8 1.1 v pwm oscillator (pwm pin) high-level output voltage v oh (pwm) 2.75 3.0 3.25 v low-level output voltage v ol (pwm) 1.2 1.35 1.5 v external capacitor charge current 1chg pwm = 2.1v -60 -45 -30 a oscillator frequency f (pwm) c = 1000pf 20 25 30 khz amplitude vp-p (pwm) 1.25 1.65 2.05 v p-p hp pin output saturation voltage vhpl i o = 7ma 0.15 0.5 v output leakage current ihpleak v o = 13.5v 10 a continued on next page.
lb11600jv no.8321-3/30 continued from preceding page. rated value parameter symbol conditions min. typ. max. unit motor constraint protection circuit block (csd and cset pins) csd saturation voltage vscsd i 0 = -0.5ma, v cc -vcsd 0.1 0.3 v csd off voltage vcsdof 0.55 0.6 0.65 v csd voltage vcsd cset = 4.9v 4.7 4.9 v cset pin current icset cset = 4.8v 35 50 65 a cset pin on voltage vcseton v cc - cset pin 0.1 0.3 v cset pin off voltage vcsetoff v cc - cset pin 0.6 0.7 0.85 v current limiter circuit (rf pin) limiter voltage vrf 0.216 0.24 0.264 v rfgnd pin current irfgnd rfgnd = 0v -60 -40 -20 a undervoltage protection circuit operating voltage vsdl 3.6 3.8 4.0 v release voltage vsdh 4.1 4.3 4.5 v hysteresis vsd 0.35 0.5 0.65 v thermal shutdown circuit (thermal protection circuit) thermal shutdown temperature tsd design target value (junction temperature)* 150 170 c hysteresis tsd design target value (junction temperature)* 25 c ceg pin ceg pin current iceg ceg = 4.8v 35 50 65 a ceg pin on voltage vcegon v cc - cset pin 0.1 0.3 v ceg pin off voltage vcegoff v cc - cset pin 0.6 0.7 0.85 v cr pin high-level output voltage v oh (cr) 3.12 3.4 3.68 v low-level output voltage v ol (cr) 0.67 0.75 0.83 v clamp voltage vclp (cr) 1.3 1.45 1.6 v fv pin charge current ichg1 fv = 2.5v -420 -300 -230 a discharge current ichg2 fv = 1v 1.3 2.5 5.0 ma fv pin high-level voltage vofvh i o = -200 a 4.7 4.9 v fv pin low-level voltage vofvl i o = 200 a 0.15 0.3 v s/s pin high-level input voltage v ih (ss) 2.0 v low-level input voltage v il (ss) 1.0 v input open voltage v io (ss) v cc -0.5 v cc v hysteresis v is (ss) 0.2 0.3 0.4 v high-level input current i ih (ss) s/s = 5v -10 0 10 a low-level input current i il (ss) s/s = 0v -130 -96 a f/r pin high-level input voltage v ih (fr) 2.0 v low-level input voltage v il (fr) 1.0 v input open voltage v io (fr) v cc -0.5 v cc v hysteresis v is (fr) 0.2 0.3 0.4 v high-level input current i ih (fr) f/r = 5v -10 0 10 a low-level input current i il (fr) f/r = 0v -130 -96 a *: these are design target value and are not tested. continued on next page.
lb11600jv no.8321-4/30 continued from preceding page. rated value parameter symbol conditions min. typ. max. unit pwmin pin high-level input voltage v ih (pwmin) 2.0 v low-level input voltage v il (pwmin) 1.0 v input open voltage v io (pwmin) v cc -0.5 v cc v hysteresis v is (pwmin) 0.2 0.3 0.4 v high-level input current i ih (pwmin) pwmin = 5v -10 0 10 a low-level input current i il (pwmin) pwmin = 0v -130 -96 a input frequency f (pwmin) 50 khz pwmre pin pwmre pin current ipwmire pwmre = 0v -260 -200 -140 a threshold voltage pwmr eth 1.12 1.25 1.38 v hysteresis pwmrehys 0.44 0.7 1.1 v package dimensions unit : mm (typ) 3191c pin assignment gnd pwmre f/r lb11600jv rf wh wl vh uh csd ctl+ pwm ul in1+ in1- vl 9 8 7 6 5 4 3 2 1 10 11 12 13 14 15 27 26 28 24 23 25 21 29 22 30 19 18 20 16 17 in2+ in2- in3+ in3- hp toc fv cr ceg cset ctl- pwmin v cc s/s rfgnd top view sanyo : ssop30(275mil) 9.75 5.6 7.6 0.22 0.65 (0.33) 1 30 0.5 0.15 1.5 max 0.1 (1.3)
lb11600jv no.8321-5/30 block diagram and application circuit 1 : mos transistor drive (low side pwm) , speed control feedback application
lb11600jv no.8321-6/30 application circuit 2 : bipolar transistor (high side pwm)
lb11600jv no.8321-7/30 truth table ? three-phase logic truth table (in = h means that the input is in the in+ > in- state.) f/r=[l] f/r=[h] output in1 in2 in3 in1 in2 in3 pwm fixed 1 h l h l h l vh ul 2 h l l l h h wh ul 3 h h l l l h wh vl 4 l h l h l h uh vl 5 l h h h l l uh wl 6 l l h h h l vh wl when f/r is low, the ic recognizes the states where the hall inputs in the above table occur in the order 1 6 as forward rotation, and the reverse order as reverse rotation. when f/r is high, the ic recognizes the states where the hall inputs in the above table occur in the order 6 1 as forward rotation, and the reverse order as reverse rotation. ? s/s pin input state operating state high or open stop state l start state if the s/s pin is not used, the input must be held at the low-level voltage.
lb11600jv no.8321-8/30 pin functions pin number function function equivalent circuit 1 2 3 4 29 30 vh vl uh ul wh wl outputs. these are push-pull outputs. duty control is applied to the uh, vh, and wh pins. internal 50k leakage protection resistors between the outputs and ground are provided to protect against output leakage in standby mode. 5 6 7 8 9 10 in1+ in1- in2+ in2- in3+ in3- hall effect sensor inputs from each motor phase. the logic high state corresponds to the state where in+ > in-. if input is provided from a hall ic, the common mode input range can be expanded by biasing either the + or - input. 11 f/r forward/reverse switching input. 12 hp hall signal single-phase output. (this pin is an open-collector output.) this pin outputs a signal that is inverted from the signal formed from the in3 input. 13 ceg rotation pulse edge detection input. (this input is used by the one-shot multivibrator circuit.) insert a capacitor between this pin and v cc . continued on next page. 1 3 29 2 4 30 v cc 50k uh, vh, wh ul, vl, wl v cc 6 8 10 5 7 9 300 300 in+ in- v cc 50k 3.5k 11 f/r v cc 12 hp 24 13 v cc 300 v cc ceg
lb11600jv no.8321-9/30 continued from preceding page. pin number function function equivalent circuit 14 cr one-shot multivibrator pulse width setting. insert a resistor between this pin and v cc and a capacitor between this pin and ground. if unused: short to ground. 15 fv hall signal one-shot multivibrator output. if unused: leave open. 16 17 ctl+ ctl- ctl+: control voltage input (integrating amplifier noninverting input) ctl-: control voltage input (integrating amplifier inverting input) 18 toc pwm waveform comparator (integrating amplifier output) continued on next page. v cc 14 24 300 v cc cr v cc 15 300 fv v cc 300 17 16 300 ctl+ ctl- v cc toc 18 40k 38 300 pwm pin 38
lb11600jv no.8321-10/30 continued from preceding page. pin number function function equivalent circuit 19 pwm pwm oscillator frequency setting. insert a capacitor between this pin and ground. 20 csd motor constraint protection detection sense input. insert a capacitor between this pin and v cc and a resistor between this pin and ground. 21 cset motor constraint protection circuit rotation input pulse detection. insert a capacitor between this pin and v cc . 22 pwmre pwm input reset. insert a resistor and a capacitor between this pin and ground. 23 pwmin external pwm input. when the input is low, the out put will be in the drive state and when the input is high or open, the output will be off. continued on next page. v cc 2k 200 19 pwm v cc 300 20 24 v cc csd 24 21 v cc 300 v cc cset v cc 300 22 pwmre v cc 50k 3.5k 23 pwmin
lb11600jv no.8321-11/30 continued from preceding page. pin number function function equivalent circuit 24 v cc v cc power supply connection. 25 s/s start/stop control. a low level sets the ic to the start state and a high level or open sets it to the stop state. 26 gnd ground connection 27 28 rfgnd rf rfgnd: output current detection circuit comparator reference ground. rf: output current detection. insert a resistor with a low resistance between the rf pin and ground. the maximum output current is set to i out = 0.24/rf by the resistor rf. v cc 50k 3.5k 25 s/s 27 v cc 6k 5k 28 rf rfgnd
lb11600jv no.8321-12/30 timing charts (hall input/output , startup, input off state, and constraint protection timing charts) in1 in2 in3 f/r = ?l? uh vh wh f/r = ?h? ul vl wl the gray areas indicate pwm output. forward uh vh wh ul vl wl in1 in2 in3 forward
lb11600jv no.8321-13/30 startup timing chart (when a buffere d input is provided to ctl+) output on pwmre vthh=1.25v 0v pwmre pwmin the pwm and toc duty signal toc trset 5v v cc pwm 0.7v csd uh (when the output is on.) 4.9v 4.9v 4.2v hysteresis = 0.7v pwmre(off)vthl=0.5v 3.8v or higher - rapid charging off.
lb11600jv no.8321-14/30 startup timing chart (when the pwmin input is used) output on pwmre vthh=1.25v 5v pwmre pwmin the pwm and toc duty signal toc trset 5v v cc pwm 0.7v csd uh (when the output is on.) 4.9v 4.9v 4.2v hysteresis = 0.7v pwmre(off)vthl=0.5v 3.8v or higher - rapid charging off.
lb11600jv no.8321-15/30 input off state (ctl+input) r eset operation timing chart output off pwmre vthh = 1.25v 0v pwmre pwmin the pwm and toc duty signal toc toff 5v v cc pwm 0.7v csd uh (when the output is on.) 4.9v 4.9v 4.2v hysteresis = 0.7v pwmre (off) vthl = 0.5v constraint protection vth = 0.6v
lb11600jv no.8321-16/30 input off state (pwmin input) reset operation timing chart output off pwmre vthh = 1.25v 0v pwmre pwmin the pwm and toc duty signal toc toff 5v v cc pwm 0.7v csd uh (when the output is on.) 4.9v 4.9v 4.2v hysteresis = 0.7v constraint protection vth = 0.6v pwmre (off) vthl = 0.5v
lb11600jv no.8321-17/30 constraint protection state latch release timing chart (clt+ input) constraint protection operation (output off) pwmre vthh = 1.25v 0v pwmre pwmin the pwm and toc duty signal toc tchg 5v v cc pwm 0.7v csd uh (when the output is on.) 4.9v 4.9v 4.2v hysteresis = 0.7v pwmre (off) vthl = 0.5v constraint protection vth = 0.6v tchg: csd voltage rise time torc latch released toff torc: output off latch state
lb11600jv no.8321-18/30 constraint protection timing chart
lb11600jv no.8321-19/30 lb11600jv application circui t diagram (fet driver: low side pwm control) *: the resistor, capacitor, and transist or values shown are for reference purposes only. the values used in an application will depend on the motor used and the control specifications. ilb01741 top view vm wl 30 vh 1 wh 29 vl 2 rf 28 uh 3 rfgnd 27 ul 4 gnd 26 in1+ 5 s/s 25 in1- 6 v cc 24 in2+ 7 pwmin lb11600jv 23 in2- 8 pwmre 22 in3+ 9 cset 21 in3- 10 csd 20 f/r 11 pwm 19 hp 12 toc 18 ceg 13 ctl- 17 cr 14 ctl+ 16 fv 15 wl 1000pf 1k wh 200 vl 1k vh 200 ul 1k uh 200 10 1000pf 3300pf 3300pf 5v 33 f 0.033 f 0.022 f 10 f 200k 150k 51k 100k 1000pf 1k 1000pf 1k 680 680 680 0.055 (2w)
lb11600jv no.8321-20/30 lb11600jv operation 1. output drive circuit the lb11600jv adopts direct pwm drive to minimize power loss in the output syst em. the output transistors are always saturated when on and the motor drive power is adjusted by changing the output on duty. output pwm switching is applied the uh, vh, and wh output side circuits. since the ul to wl and uh to wh outputs have the same output configuration, either low side pwm or high side pwm drive can be implemented by using appropriate circuit structures with the external output drive transistor s. since the reverse recovery time for th e diodes connected to the non-pwm side outputs can be a problem, care is required in selecting these di odes. (if diodes with a short reverse recovery time are not used, through currents will flow at the instan t the pwm side transistors are turned on.) the ul to wl and uh to wh outputs go to the high-impedan ce state in the stopped state and when the supply voltage is extremely low (i.e. lower than the allowable operating vo ltage). this means that workarounds (such as pull-down resistors) are required so that leakage cu rrents and other phenomenon do not cause incorrect operation in external circuits. 2. power saving circuit the lb11600jv goes to a power saving state in which power consumption is reduced when the s/s pin is set to the high level. the power saving state cuts off the bias current from most of the circuits in the ic. 3. notes on the pwm frequency the pwm frequency is set by the capacitance of the capacitor (c) connect ed to the pwm pin. the formula for calculating the pw m frequency is shown below. formula (when v cc = 5v (typical)) oscillator period: t = t1 + t2 (s) threshold voltage: v1 = 0.25 v cc + 0.0975 = 1.35 (v) v2 = 0.6 v cc = 3.0v (v) charge time: t1 = c (v2 - v1)/ic (s) ic: charge current provided by the pwm pin: 45a discharge time: t2 = - c rin ln (v1/v2) (s) rin: pwm pin internal discharge resistor (2k ) c: external capacitor oscillator frequency: fpwm = 1/t (hz) if a 1000pf capacitor is used, the oscillator frequency will be about 25khz. if the pwm frequency is too low, the motor may emit audible switching noise, and if it is too high, power loss in the output circuits will be excessive. we recommend using a frequency in the range 15 to 50khz. connect the ground si de of the external capacitor as close as possible to the ic gnd pin to minimize the influence of output noise and other problems. t2 t1 v1 v2
lb11600jv no.8321-21/30 4. notes on pwm drive methods the output duty can be controlled by any of the following methods. ? control by comparing the toc pin voltage with the pwm oscillator waveform this method sets the uh, vh, and wh output duty by comparing the toc pin voltage with the pwm oscillator waveform. when the toc pin voltage falls below 1.35v (typical), the duty will be 0%, and when it rises above 3.0v (typical), the duty will be 100%. since the toc pin is the cont rol amplifier's output pin, it is not possible to directly input a control voltage to the toc pin. therefore, the control amplif ier is normally used as a buffer amplifier (by connecting the ctl- pin to the toc pin) and inputting a dc voltage to the ctl+ pin. (this causes the toc pin voltage to become the same as the ctl+ pin voltage.) in this case, the output duty will increase as the ctl+ pin voltage becomes higher. since the motor will be driven if the ctl+ pin is in the open state, a pull-down resistor must be connected to the ctl+ pin if it is not desirable to drive the motor when the input is in the open state. if the ctl+ pin is used for motor control, set the pwmin pin to the low level or short it to ground. ? pulse control using the pwmin pin a pulse input can be applied to the pwmin pin and the duty of that signal used to control the output. when a low-level input voltage is applied to the pwmin pin the output will be on, and when a high-level input voltage is applied the output will be off. when the pwmin pin is open, it goes to the high level and the output will be turned off. if the inverse input logic is required, use an external npn transistor as shown in the figure. if the pwmin pin is used for control, connect the ctl- pin to ground and connect the ctl- pin to the toc pin. a 1000pf capacitor must be connected to the pwm pin even when the pwmin pin is used for control. ? pwmre pin input pulse reset to prevent incorrect operation of the constraint protection circuit when the v cc power supply is started or when the motor is stopped (the constraint protection circuit will operat e immediately if the csd pin potential is low), that is to assure that the csd pin is set to the high-level voltage reliably (by assuring the capacitor charge time), a reset period (outputs off, the rapid charge time for the csd pin) is set up by a resistor and capacitor connected to the pwmre pin. when the motor is controlled by either the ctl+ pin or by pulses input to the pwmin pin, output to the motor is not provided immediately. rather the output remains in the off state (the reset period) until the charge/discharge potential due to the on/off operation set by the input pulse duty width, th e pwmre pin charge current, an d the capacitor and resistor connected to the pwmre pin rises above 1.25v (typical). the ic enters operating mode when the pwmre potential is over 1.25v (typical), and the output goes to the off state (reset state) when the pwmre potential falls below 0.55v (typical) in the input pulse off state. the ic operates with the outputs on (uh, vh, and wh), wh en the pwmre potential is over 1.25v (typical) and the csd pin potential is over 0.76 v cc (3.8v typical when v cc = 5v). see the timing chart for startup and the input off state. the formula for setting the reset time (trest) and the timing charts are shown on the following pages. the rise potential (v1) and the fall potential (v2) due to the on/off duty ratio when a pwmin input is used: when on: v1 = (v0 - ipwmre r) e-t1/rc + ipwmre r when off: v2 = v1 e-t2/rc = v ipwmre: pwmre pin charge current: 200a (typical) v0: pwmre initial potential: 0v c: pwmre pin external capacitor r: pwmre pin external resistor t1: pwmin input duty on time t2: pwmin input duty off time to the pwmin pin pulse input
lb11600jv no.8321-22/30 the time (n times the pwmin period) required for the potentia l, which is increased by th e v2 potential difference ( v) on each input pulse, to exceed the threshold voltage (vth = 1.25v) is the reset period (trest). v2 + v + v ??? 1.25v trest tpwmin n (s) v cc = 5v, pwmin = 25khz, on duty ratio = 20% pwmre: c = 2200pf, r = 180k pwmin = 25khz = 40 s t1 = 40 s 0.2 = 8 s t2 = 40 s 0.8 = 32 s v1 = (v0 - ipwmre r) e-t1/rc + ipwmre r = (0 - 200 a 180k ) 0.98 + (200 a 180k ) = - 35.28 + 36 = 0.72 (v) v2 = v1 e-t2/rc = 0.72 0.922 = 0.664 (v) since v (0.644) is added on each pwmin input pulse, and v2 + v = 0.664 + 0.664 1.25v the threshold voltage (1.25v) will be exceeded on the second pulse. from the formula for the on time: t1' = cr ln ((v0 ? ipwmre r)/(v1 - ipwmre r)) since the potential difference with respect to 1.25v due to th e rise potential v2 of the second pwmin pulse is 1.25 - 0.664 = 0.586v, 1.25v will be exceeded in the on du ty state. therefore, t1' = 2200pf 180k ln ((0.664 ? 200 a 180k ) / (1.25 ? 200 a 180k )) = 396 s ln (35.336/34.75) = 6.622 s (s) thus the reset time trest will be one pwmin period plus t1'. trest = 40 s + 6.622 s = 46.622 s (s)
lb11600jv no.8321-23/30 pwmre timing chart for pwmin pin input output on pwmre pwmin trset csd uh (when the output is on.) 4.9v 4.2v toc pwm hysteresis = 0.7v v 5v pwmre vthh=1.25v 4.9v pwmre(off)vthl=0.5v 3.8v or higher - rapid charging off. v0 v1 v2 v t1 t2
lb11600jv no.8321-24/30 1. ctl+ input mode (when the toc potential is higher than the pwm triangle wave rise) the rise potential (v1) and fall potential (v2) due to the on /off duty due to the toc potential and the pwm triangle wave when on: v1 = (v0 - ipwmre r) e-t1/rc + ipwmre r when off: v2 = v1 e-t2/rc when the toc potential rises and the pwm triangle wave rise is slow, the ic will be in the on duty state at startup. this results in the time tpwmra, which is the time until the pwm triangle wave low level is reached. the potential difference due to each input pulse is: v = v2 - vpwmra. vpwmra = (ipwm tpwmra) / cpwm ipwm: pwm pin charge current: 45a (typical) cpwm: capacitance of the pwm pin external capacitor ipwmre: pwmre pin charge current: 200a (typical) v0: pwmre pin initial potential: 0 v c: capacitance of the pwmr e pin external capacitor r: resistance of the pwmre pin external resistor t1: pwmin pin input duty on time t2: pwmin pin input duty off time the time (n times the pwmin period) required for the potentia l, which is increased by th e v2 potential difference ( v) on each input pulse, to exceed the threshold voltage (vth = 1.25v) is the reset period (trest). v2 + v + v ??? 1.25v trest tpwmin n + tpwmra (s) 2. ctl+ input mode (when the toc potential rises after the pwm triangle wave rises) the time required for the sum of the potentials due to the times set for each on/off duty ratio fo r the rise time to exceed the threshold voltage (1.25v) becomes the reset time (trest). the times t1 and t2 for the rise potentia l (v1) and fall potential (v2) due to each on duty ratio will differ. thus these must be calculated individually for each input pulse signal. the fo rmulas for calculating v1 and v2 are the same as for the pwmin input case.
lb11600jv no.8321-25/30 pwmre timing chart for ctl+ buffered input (1) ctl+ input mode (when the toc potential is hi gh due to the rise of the pwm triangle wave) output on trset csd uh (when the output is on.) 4.9v 4.2v hysteresis = 0.7v 0v pwmin the pwm and toc duty signal toc pwm 0.7v pwmre vthh=1.25v pwmre 4.9v pwmre(off)vthl=0.5v 3.8v or higher - rapid charging off. v0 v2 v1 tpwmra t2 t1
lb11600jv no.8321-26/30 pwmre timing chart for ctl+ buffered input (2) ctl+ input mode (when the toc potential ri ses after the rise of the pwm triangle wave) output on trset csd uh (when the ou t put is on.) 4.9v 4.2v hysteresis = 0.7v 0v pwmin the pwm and toc duty signal toc pwm 0.7v pwmre vthh=1.25v pwmre 4.9v pwmre(off)vthl=0.5v 3.8v or higher - rapid charging off. v0 v0 v1 v2 v3 v4 t1 t2 t3 t4 t5 v5
lb11600jv no.8321-27/30 5. hall input signals the hall effect sensor inputs require input signals with an amplitude larger than the hysteresis (80mv maximum) and an even larger amplitude is desirable to av oid problems due to noise, phase displacemen t, and other issues. if disturbances to the output waveforms (at phase switching) or hp output occur due to noise, the disturbances must be prevented by inserting capacitors across the inputs or by other means. the hall inputs are used as input discrimination signals to the constraint protection circuit and the one-shot multivibrator ci rcuit. although these circuits are designed to tolerate a certain amount of noise, care is required if these protection circuits are used. if all three phases of the hall input signals go to the same state, all of the outputs will be turned off (a ll of the ul, vl, wl, uh, vh, and wh outputs will go to the low level potential). if the outputs from a hall ic are used for these inputs, tying one side of the inputs (either the + or - side) to a voltage wit hin the common-mode input range for when hall sensors are used allows the other side of the input to be used with an input in the 0 to v cc range. 6. undervoltage protection circuit this ic starts up (output operation turns on) at a v cc voltage of 4.3v (typical) and turns the outputs off (sets the uh, vh, and wh outputs to the low level potential) when the v cc voltage falls to under 3.8v(typical). 7. constraint protection circuit the lb11600jv includes a constraint protection circuit to protect the motor and the ic itself when the motor is physically prevented from turning. if the hall input signals do not change for a certain fixed period when the ic is operating in the motor drive state, one side of the output system (the uh, vh, and wh outputs) is turned off. the time is set by the discharge time of the resistor and capacitor connected to the csd pin. (see the constraint protection circuit timing chart.) the motor rotation pulse detection signal is detected with the timing of the fall (high to low) of the uh output signal, one of the three output phases. the rotation pulse detection signal time is set by the discharge time for the cset pin capacitor. during motor rotation, the csd pin potential will always be high during the rotation pulse detection time. if the motor becomes constrained (stopped), the csd potential is discharged and the outputs (uh, vh, and wh) are set low when the csp potential falls under 0.6v. after the constraint protection circuit operates, the outputs will be latched in the low state. to clear this latched state, se t either pwmin or s/s to the high level. the latched state is cleared when the pwmre potential falls be low 0.55v (typical) and the ic enters the reset state. (see the latch clear timing chart.) note that if the csd pin resistor rc is too large, the csd pi n potential may rise due to the bias current from the internal comparator circuit. rotation pulse detection signal time: tps = cs vbe / icset (s) cs: cset pin external capacitor (c onnected between vcc and cset) vbe: vbe for the transistor in the cons traint protection circuit: 0.7v (typical) lcset: cset pin discharge current: 50a (typical) motor constraint time: tcsd = ln (v cc / (0.6 - ibcd rc) cc rc (s) cc: csd pin external capacitor (connected between v cc and csd) rc: csd pin external resistor (connected between the csd pin and ground) ibcd: csd pin internal comparat or bias current: 1a (typical) csd pin discharge potential threshold voltage: 0.6v (typical) latch release time: toff = ln (v cc / 0.55) cre rre (s) cre: pwmre pin external capacitor (conn ected between the pwmre pin and ground) rre: pwmre pin external resistor (conn ected between the pwmre pin and ground) csd potential rise time (rapid charging time): tchg cc rc ln ((v1 - ic rc) / (v2 - ic rc)) (s) cc: csd pin external capacitor (connected between v cc and csd) rc: csd pin external resistor (connected between the csd pin and ground) ic: csd pin transistor current (7ma maximum (design target value)) v1: csd pin initial voltage v2: csd pin voltage (when the transistor is in the on state): 4.9v (typical)
lb11600jv no.8321-28/30 csd voltage rise time (during motor rotation): tchg cc rc ln((v1 - ic rc) / (v2 - ic rc)) (s) cc: csd pin external capacitor (connected between v cc and csd) rc: csd pin external resistor (connected between the csd pin and ground) ic: csd pin transistor current (3.5ma maximum (design target value)) v1: csd pin initial voltage v2: csd pin voltage (when the transistor is in the on state): 4.9v (typical) when v cc = 5v, to set the motor constraint time to 3 seconds: use a 10f capacitor for the csd pin capacitor cc and a 130k resistor for rc. motor constraint time: tcsd = 1n (5 / (0.6 ? 130k 1 a) 10 f 130k = 2.36 10 f 130k = 3.068 (s) the discharge time for the capacitor specified above will be the motor constraint time. the pulse signal that detects whether or not the motor is turning is set by the cset pin capacitor. if a 0.022 f capacitor is used as the cset pin capacitor cs: rotation pulse signal detection time: tps = 0.022 f 0.7/50 a = 308 s note that care is required in setting these values since the amplitude of the rotation pulse detection signal is influenced by the motor speed, and the csd capacitance. if the rotation pulse detection signal time is too short, the ic will not be able to raise the csd potential to the high level. also, if the csd pin capacitor value is too small and the discharge time too short, the rotation detection pulse signal will not be issued for the motor rotation period at the start of motor rotation (when the motor is turning slowly), and the constraint protection circuit may latch. for example, since at speeds under 100rpm the uh output period will be 300ms, the motor constraint time must be set to a time of at least 600ms. 8. overcurrent protection circuit the overcurrent protection circuit limits the output current to be a maximum of i = vrf/rf (where vrf = 0.24v typical, and rf is the current detection resistor). the current limiter circuit detects the reverse recovery current in the output diodes due to pwm opera tion and includes a built-in filter circuit to prevent incorrect operation. while this internal filter ci rcuit is adequate for most applications, if the circuit is observed to operate incorrectly (for example, in cases where the diode reverse recovery current flows for over 3 s), an external filter circuit (such as a passive low-pass filter circuit) must be added. 9. thermal protection circuit the thermal protection circuit turns off one side of the out put (uh, vh, and wh) if the ic junction temperature (tj) exceeds the stipulated temperat ure (tsd = 170c, typical). 10. direction reversal do not reverse motor direction while the motor is turning. to reverse directions, first stop the motor (set pwmin high or set the s/s pin high) and then startup again with the desired direction. 11. hp output the hall signal created from the in3 pin hall amplifier input signal is inverted and output from the hp pin. since the hp pin is an open-collector output, a pull-up resistor must be inserted between v cc and the hp pin. hall amplifier input conditions: in3-: fixe d potential, hp pin: pulled up to v cc . current detection resistor to the rf pin in3- in3+ input hp pin
lb11600jv no.8321-29/30 12. one-shot multivibrator circuit block (ceg, cr, and fv pins) the lb11600jv includes a built-in one-shot multivibrator circu it to allow it to support speed feedback control. the signal used for speed control is a rotation pulse detection signal that is created in the ceg pin circuit block with the timing of the fall (high to low) of the uh output signal, one of the thr ee output phases. the lb11600jv detects the rotation period from this signal. the rotation pulse detection signal time is set by the discharge time of the capacitor connected to the ceg pin. rotation pulse detection signal time: tps = ce vbe/iceg (s) ce: ceg pin external capacitor (connected between v cc and ceg) vbe: vbe for the transistor in the ceg edge detection circuit: 0.7v (typical) iceg: cset pin discharge current: 50a (typical) the cr pin sets the pulse width (high period) generated at the fv pin at each signal from the ceg pin. the pulse width is set by connecting a re sistor and a capacitor between the cr pin and v cc and ground, respectively. the pulse width trc can be calculated approximately with the following formula. trc 1.1 r c (s) normally, a smoothing circuit consisting of a resistor and capacitor as shown in the figure is connected to the fv pin. a resistor with a value of at least 25k must be selected. the value of the capacitor must be selected so that adequate smoothing of the fv voltage is provided when the motor speed is low. normally, this circuit is set up so that the following relationship holds when fuh (hz) is the uh output frequency at the highest motor speed. trc 1/(2 fuh) (s) in this case, the fv voltage will change from 0 to about 5v according to the motor speed. if the fv output is not used, connect the cr pin to ground and leave the fv pin open. 13. power supply stabilization since the lb11600jv adopts a switching-based drive method, the power supply line level is eas ily disturbed. therefore it is necessary to connect a capacito r with adequate capacitance to stabilize the power supply between the v cc pin and ground. if diodes are inserted in the power supp ly lines to prevent damage if the power supply is inadvertently connected with reverse polarity, the power supply line will be even more sensitiv e to disruption. here, an even larger capacitance must be provided. if the switch and the capacitor are widely separated when the pow er supply is turned on and of f, such as during switching, the supply voltage may swing widely due to the surge current between the line inductance and the capacitor. voltages that exceed the lb11600jv's voltage handling cap acity may occur. in applications such as this, do not use components, such as ceramic capacitors, which have a low capacitor series impe dance, but rather use electrolytic capacitors and implement measures to minimize the surge curr ent and prevent voltage increases. fv v o l t age fv pin to the v cc pin cr pin r c
lb11600jv ps no.8321-30/30 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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